(1) Field of the Invention
The present invention generally relates to an output buffer circuit and more particularly to an output buffer circuit capable of stably outputting, to a transmission line, a signal in which a high level is changed to a low level and vice versa at a high speed.
Small-amplitude interfaces, such as the so called CTT (Center Tap Terminal) and T-LVTTL(Terminated LVTTL), are used as high-speed I/O interfaces for CMOS devices. In such interfaces, high-speed input/output operations between a CPU (Central Processing Unit) and memories are required, so that impedance matching between the CPU side devices and the memory side devices are needed to process signals at a high speed.
(2) Description of the Related Art
FIG. 1 shows a conventional output buffer circuit which is used in the small-amplitude interface such as the CTT.
Referring to FIG. 1, a device 210, such as a CPU or a memory device, includes an output buffer circuit 211. The output buffer circuit 211 has a p-type FET 215 (MOSFET) and an n-type FET 216 (MOSFET). The source (S) of the p-type FET 215 is connected to a power line V.sub.cc. The source (S) of the n-type FET 216 is connected to a ground line V.sub.ss. The gates (G) of the p-type FET 215 and the n-type FET 216 are connected to each other, and the drains (D) thereof are connected to each other. Signals are input to the gates (G) of the p-type FET 215 and the n-type FET 216. Signals from the drains (D) of the p-type FET 215 and the n-type FET 216 are supplied, as output signals of the output buffer circuit 211, to a bus line 225 (a signal transmission line) which is terminated by a terminating resistor R.sub.t 226 connected to a power line V.sub.tt. The voltage of the power line V.sub.tt is approximately half of that of the power line V.sub.cc (V.sub.tt =1/2V.sub.cc). Devices 222, 223 and 224, such as memories, are connected to the bus line 225.
The above circuit including the conventional output buffer circuit 211 is operated as follows.
In a case where the device 210 should output a signal having a high level (referred to as an H-level signal), a signal having a low level (referred to as an L-level signal) is input to the gates of the p-type FET 215 and the n-type FET 216. In this case, the p-type FET 215 is in an ON state and the n-type FET 216 is in an OFF state. As a result, the H-level signal is output from the output buffer circuit 211. At this time, a current flows from the power line V.sub.cc to the power line V.sub.tt through the source (S) of the p-type FET 215, the drain (D) of the p-type FET 215, the bus line 225 and the terminating resistor R.sub.t 226.
In a case where the device 210 should output an L-level signal, an H-level signal is input to the gates of the p-type FET 215 and the n-type FET 216. In this case, the p-type FET 215 is in the OFF state and the n-type FET 216 is in the ON state. As a result, the L-level signal is output from the output buffer circuit 211. At this time, a current flows from the power line V.sub.tt to the ground line V.sub.ss through the terminating register R.sub.t 226, the drain (D) of the n-type FET 216 and the source (S) of the n-type FET 216.
In the conventional output buffer circuit 211 as described above, there is a relationship, as shown in FIG. 2(a), between the input signal (IN) and the output signal (OUT). A node at which the drains (D) of the p-type FET 215 and the n-type FET 216 are connected is an output terminal of the output buffer circuit 211. Thus, even if the input signal (IN) varies as shown in FIG. 2(a), a voltage V.sub.gs between the gate (G) and the source (S) of each of the FETS 215 and 216 is maintained at a constant level. As a result, the output resistance R.sub.out of the output buffer circuit 211 is constant as shown in FIG. 2(b). The output resistance R.sub.out is designed so that the level of the output signal (OUT) responsive to the input signal (IN) as shown in FIG. 2(a) satisfies conditions of the small-amplitude interface such as the CTT. In this case, the output resistance R.sub.out (e.g. 70.OMEGA.) is generally greater than an impedance (e.g. 30.OMEGA.) of the bus line 225 (referred to as a line impedance Z) as shown in FIG. 2(b).
In addition, various devices such as the memories may be connected to the bus line 225. In this case, due to the impedances of the devices connected to the bus line 225, the line impedance Z is further lowered. Furthermore, for example, SIMMs (Single In-line Memory Modules) each of which is a printed circuit board provided with DRAMs may be detachably connected to the bus line 225. That is, the number of SIMMs may be varied, so that the line impedance Z may be varied.
As has been described above, the output resistance R.sub.out of the output buffer circuit 211 is higher than the line impedance Z which may be varied in accordance with the number of devices connected to the line to which signals are output from the output buffer circuit 211. Thus, it is difficult to make the matching between the output resistance R.sub.out and the line impedance Z.
In a case where the matching between the output resistance R.sub.out of the output buffer circuit 211 and the line impedance Z are not made, the waveform of the output signal is distorted in the level transition (the high level to the low level and vice versa) of the output signal. The waveform distortion of the output signal results from signal reflection at the terminating resistor and the devices connected to the line.
In a case where the frequency of the output signal from the output buffer circuit 211 is relatively low, the waveform distortion of the output signal in the level transition is inconspicuous. However, in a case where the frequency of the output signal from the output buffer circuit is relatively high, the waveform distortion of the output signal is conspicuous. Thus, it is difficult to stably transmit a signal output from the conventional output buffer circuit through the transmission line at a high speed.